The present invention relates to multi-graphics processor systems, and more particularly to accessing a common memory from multiple graphics processors.
Graphics processors are used to render images based upon data and/or commands issued by a system processor. Multiple graphics processors have been used in order to improve the rate at which graphics data has been rendered. By dividing the rendering workload among multiple independent graphics processors, the workload of rendering graphics is multiplexed, resulting in a system capable of rendering images at a greater rate. However, because of the independent nature of multiple graphics processors used in the prior art, certain efficiencies based upon reuse of rendered data are lost. In some instances, a specific use of multiple graphics processors partitions the rendering tasks of one or several frames into separate portions to be distributed among separate processors. However, a problem occurs when the system bus, system software, or rendering software is not capable of supporting multiple graphics devices. Another problem occurs when devices being connected through a bridge support different aspects of various protocols.
Therefore, a system and/or method capable of multiplexing the rendering of images, while maintaining efficiencies associated with the reuse of rendered data would be advantageous.